Review of curvilinear masks for chip lithography covers five key technology areas
Curvilinear masks, derived from inverse lithography, remove 90-degree corners that amplify mask errors and widen the process window at advanced nodes, according to the review authors.
A review published in Light Advanced Manufacturing (DOI 10.37188/lam.2026.106) and released on 10 November 2026 describes curvilinear mask technology for integrated circuit lithography doi.org
Light Advanced Manufacturingdoi.orgOpen source ↗. The paper, by Tie Jun Cui et al., covers the underlying principles, advantages in manufacturing and design, application scenarios and current challenges. It also reviews five key enabling technologies.
Curvilinear masks and the process window
Traditional chip layouts use strictly horizontal and vertical lines, known as orthogonal or Manhattan structures. The 90-degree corners in them are highly sensitive to manufacturing fluctuations, easily amplify mask errors and lead to failures. At advanced nodes, lithography also faces diffraction limits, equipment bottlenecks and random process variations.
Curvilinear masks derive from inverse lithography technology (ILT), which treats mask design as a mathematical inverse optimization problem. Its solution gives free-form curved shapes that follow optical physical laws. On the manufacturing side, such masks eliminate unstable sharp corners, spread errors evenly and widen the process window.
On the design side, curved routing breaks the limits of orthogonal space, and bottom-layer metals can connect nodes by the shortest paths. According to the authors, this compresses cell area, reduces the need for upper metal layers and vias, and lowers wafer costs doi.org
Light Advanced Manufacturingdoi.orgOpen source ↗.
Five enabling technologies
In layout design, non-orthogonal curved interconnects are introduced to bypass obstacles and relieve routing congestion. In optical proximity correction, generating curvilinear masks requires large computing power; hardware acceleration is used, and parametric curve representation balances image fidelity with data volume.
Mask rule checks have been reconfigured. Approximating curves with polygons causes precision loss and data redundancy, so a "rolling circle" check based on the minimum manufacturable circle was proposed, and native curve algorithms evaluate mathematical curves directly.
In mask writing, variable-shaped beam writers struggle with complex curves because of the explosive growth in shot counts. Multi-beam mask writers use thousands of micro-beams for pixelated scanning, so writing time does not depend on pattern complexity doi.org
Light Advanced Manufacturingdoi.orgOpen source ↗. In wafer metrology, researchers extract actual two-dimensional edges from scanning electron microscope images and have established new statistical standards for error evaluation.
Mass production still faces hurdles: full-chip optimization demands immense computing power, and polygon-based data formats cause severe data growth. The industry is upgrading data standards to support parametric curves natively. The authors point to a "Design-Mask-Wafer" co-optimization framework with metrology feedback to earlier design stages.
