Samsung Electronics plans to finish 3D Cube-H chip packaging development by early next year, report says
ZDNET Korea reports Samsung is developing hybrid-bonded 3D chip stacking with a pitch of about 6 μm, versus at least 25 μm for thermocompression bonding.
Samsung Electronics plans to complete development of its advanced packaging technology 3D Cube-H by early next year, according to a November 10 report by ZDNET Korea, relayed by IT Home and published on kucoin.com kucoin.com
kucoin.comkucoin.comOpen source ↗. The technology is still under development.
3D Cube is a packaging approach that stacks several chips vertically. Compared with the traditional horizontal arrangement of chips, it allows more transistors to be integrated within the same area. The primary application of 3D Cube-H is ultra-high-performance chips.
From thermocompression to hybrid bonding
Samsung previously developed 3D Cube-T, which uses thermocompression bonding (TC bonding). The company is now researching 3D Cube-H, which relies on hybrid bonding. Samsung has been developing 3D Cube-H with a pitch of approximately 6 μm, whereas chips using conventional TC bonding currently have a pitch of at least around 25 μm.
Design kit and customer evaluations
An industry source familiar with the situation said Samsung has been actively developing hybrid bonding for 3D system (logic) chips. According to this source, the company plans to complete its first design kit by early next year and then begin evaluations with potential customers kucoin.com
kucoin.comkucoin.comOpen source ↗.
Another semiconductor industry professional said hybrid bonding significantly increases connection density between chips and reduces energy consumption per bit, and that it offers advantages over TC bonding in thermal management. These are the source's statements; the material gives no measurements.
