# SNU team's 5 nm HZO capacitor switches at 0.6 V and shows no hard breakdown through 10^12 cycles

- Published: 2026-11-05 08:15 UTC
- Section: Machines & Making › Electronics
- Tags: ferroelectric capacitor, Hf0.5Zr0.5O2, 0.6 V switching, TiN (111) texture, speed–endurance dilemma, DRAM-class memory, 1T–1C cell, Seoul National University, Min Hyuk Park
- URL: https://realtech.media/news/rt-e8b085e11a1dd5dbc1616ab2_snu_team_s/

**Seoul National University researchers made a 5 nm hafnium zirconium oxide capacitor with saturated hysteresis at 0.6 V, a laboratory step toward low-voltage DRAM-class ferroelectric memory.**

![SNU team's 5 nm HZO capacitor switches at 0.6 V and shows no hard breakdown through 10^12 cycles](https://sgzwpqqelzmajkcubgkl.supabase.co/storage/v1/object/public/rt-media/2026/11/78a5ea8cd11adbeb.jpg)
*Steve Jurvetson, Wikimedia Commons, CC BY 2.0*

A team led by Professor Min Hyuk Park of the Department of Materials Science and Engineering at Seoul National University reported a ferroelectric capacitor based on 5 nm Hf0.5Zr0.5O2 that switches at 0.6 V. The work was done with Hanyang University, Pohang Accelerator Laboratory and Samsung Electronics, published in Nature Communications and announced on 4 November 2026. [1] The devices showed saturated hysteresis at 0.6 V, with 2Pr of 31.5 μC cm⁻² and Ec of 0.62 MV cm⁻¹, and no hard electrical breakdown through 10¹² bipolar cycles. [1]

Hafnium zirconium oxide can increase charge density in scaled capacitors, but its high coercive field limits the low-voltage, high-endurance switching that DRAM and embedded ferroelectric memories require. Faster polarization switching usually needs a higher voltage, which stresses the device and can shorten its lifetime. This is known as the speed–endurance dilemma. Thinning the film alone does not remove it, because the influence of the electrode interface grows as the film gets thinner.

## Electrode and interface engineering

The authors used plasma-engineered (111)-textured TiN electrodes with N-rich, oxidation-resistant surfaces. These surfaces suppress interfacial oxidation and enable robust switching in the 5 nm capacitors. [1] According to the researchers, this reduces voltage loss at the interface and lets polarization switch uniformly. They also report that the depolarization field, which normally weakens remanent polarization, helps lower the external voltage needed in the initial stage of polarization reversal. [1]

## Speed, endurance and cell simulation

The measured times to switch half of the polarization were 42.1 ns at 0.6 V and 8.1 ns at 1.0 V. With a criterion of less than 20% polarization loss, the device endured 600 billion cycles at 0.6 V and one trillion cycles at 1 V. [1] Switching tended to become faster as device area decreased. From the nucleation-limited switching kinetics, the authors extrapolate sub-nanosecond polarization reversal at DRAM-relevant capacitor areas. This is an extrapolation, not a measurement. [1]

The memory-cell figures come from circuit simulation. At 1.1 V, a common plate 1T–1C cell gave short- and long-term stand-by sensing margins of 482 and 201 mV under a 20 fF bit line load. [1] The authors state that, compared with previously reported ferroelectric capacitors, the combination of operating voltage, switching speed and endurance is the best reported.

## Sources

1. [Nature Communications](https://doi.org/10.1038/s41467-026-78705-4)
2. [EurekAlert](https://www.eurekalert.org/news-releases/1150404)

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Source: RealTech, realtech.media — https://realtech.media/news/rt-e8b085e11a1dd5dbc1616ab2_snu_team_s/