# Review of curvilinear masks for chip lithography covers five key technology areas

- Published: 2026-11-13 05:04 UTC
- Section: Machines & Making › Manufacturing
- Tags: curvilinear mask technology, inverse lithography technology, optical lithography, process window, optical proximity correction, mask rule check, multi-beam mask writer, wafer metrology, Manhattan layout, integrated circuit manufacturing
- URL: https://realtech.media/news/rt-87c53ead03bf5d112fe4818c_review_of_curvilinear/

**Curvilinear masks, derived from inverse lithography, remove 90-degree corners that amplify mask errors and widen the process window at advanced nodes, according to the review authors.**

![Review of curvilinear masks for chip lithography covers five key technology areas](https://realtech.media/media/2026/11/113f25803c863377.jpg)
*DrSmile Kommunikation, Wikimedia Commons, CC BY-SA 4.0*

A review published in Light Advanced Manufacturing (DOI 10.37188/lam.2026.106) and released on 10 November 2026 describes curvilinear mask technology for integrated circuit lithography [1]. The paper, by Tie Jun Cui et al., covers the underlying principles, advantages in manufacturing and design, application scenarios and current challenges. It also reviews five key enabling technologies [1].

## Curvilinear masks and the process window

Traditional chip layouts use strictly horizontal and vertical lines, known as orthogonal or Manhattan structures. The 90-degree corners in them are highly sensitive to manufacturing fluctuations, easily amplify mask errors and lead to failures [1]. At advanced nodes, lithography also faces diffraction limits, equipment bottlenecks and random process variations [1].

Curvilinear masks derive from inverse lithography technology (ILT), which treats mask design as a mathematical inverse optimization problem. Its solution gives free-form curved shapes that follow optical physical laws [1]. On the manufacturing side, such masks eliminate unstable sharp corners, spread errors evenly and widen the process window [1].

On the design side, curved routing breaks the limits of orthogonal space, and bottom-layer metals can connect nodes by the shortest paths. According to the authors, this compresses cell area, reduces the need for upper metal layers and vias, and lowers wafer costs [1].

## Five enabling technologies

In layout design, non-orthogonal curved interconnects are introduced to bypass obstacles and relieve routing congestion [1]. In optical proximity correction, generating curvilinear masks requires large computing power; hardware acceleration is used, and parametric curve representation balances image fidelity with data volume [1].

Mask rule checks have been reconfigured. Approximating curves with polygons causes precision loss and data redundancy, so a "rolling circle" check based on the minimum manufacturable circle was proposed, and native curve algorithms evaluate mathematical curves directly [1].

In mask writing, variable-shaped beam writers struggle with complex curves because of the explosive growth in shot counts. Multi-beam mask writers use thousands of micro-beams for pixelated scanning, so writing time does not depend on pattern complexity [1]. In wafer metrology, researchers extract actual two-dimensional edges from scanning electron microscope images and have established new statistical standards for error evaluation [1].

Mass production still faces hurdles: full-chip optimization demands immense computing power, and polygon-based data formats cause severe data growth. The industry is upgrading data standards to support parametric curves natively [1]. The authors point to a "Design-Mask-Wafer" co-optimization framework with metrology feedback to earlier design stages [1].

## Sources

1. [Light Advanced Manufacturing](https://doi.org/10.37188/lam.2026.106)
2. [EurekAlert](https://www.eurekalert.org/news-releases/1151402)

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Source: RealTech, realtech.media — https://realtech.media/news/rt-87c53ead03bf5d112fe4818c_review_of_curvilinear/